1. Field
Methods and apparatuses with respect to the exemplary embodiments disclosed herein relate to an image forming apparatus and chip, and more particularly, to an image forming apparatus and chip where a circuit board having a small number of layers may be used by changing the ball arrangement of a chip.
2. Description of the Related Art
An image forming apparatus generally refers to an apparatus configured to (suitable for, capable of, adapted to, etc.) print data on a printing medium (for example, printing paper), the print data being generated in a terminal such as a computer. A copier, printer, facsimile, and multi function peripheral (MFP) which combines two or more functions of a copier, printer, and facsimile in one apparatus are examples of an image forming apparatus.
Recent image forming apparatuses provide high-speed printing functions, or use systems on chip (SoC) in order to process various images. Herein, SoC may refer to a technology and product where various semiconductor components are integrated in one component.
In the case of using an SoC, the SoC is mounted on a surface of a printed circuit board (PCB) for use in an image forming apparatus. Herein, in the circuit board, a pattern may be formed to electrically connect the SoC with other devices, but since it is impossible to electrically connect all SoC with other devices using one layer, vias, that is, a plurality of layers, are used to form a pattern for electrically connecting the SoC with other devices.
Meanwhile, there are various elements determining the number of layers to be provided in a circuit board, and the most important element is generally the SoC. That is, the SoC determines the number of layers of the circuit board. The smaller the number of devices connected to the SoC, the smaller the number of vias of the pattern for electrically connecting the SoC with the devices, and thus the size area of the routing is not limited so much, and only one or two routing layers are necessary. But, when there are numerous devices connected to the SoC, the number of patterns and vias increase, thereby increasing the routing area and the number of routing layers. Thus, there is required a multi-layer PCB where a pattern layer is embedded inside, instead of a single-sided or double-sided circuit board.
Theoretically, there is no limitation to the number of layers that may be deposited in a multi-layer PCB, but the greater the number of layers deposited in a multi-layer PCB, the greater the manufacturing cost, and thus considering the product applicability and the reality, it is not practical (or efficient) to simply increase the number of PCB layers. In this regard, there is required a method for using a circuit board having a small number of layers by changing the ball arrangement of a chip.